Multiply-accumulate units (“MACs”) perform multiplication and accumulation operations in a single instruction cycle in a processor. Usually, the result of a multiplication operation is added, or accumulated to, another result stored in an accumulator, or register. These units are often used to speed up video/graphics applications as well as digital signal processor operations such as convolution and filtering.
Single instruction, multiple data (“SIMD”) style processing has been used to accelerate multimedia processing. Instruction sets for processors often include SIMD instructions where multiple data elements are packed in a single wide register, with the individual data elements operated on in parallel. One example is Intel's MMX (multimedia extension) TM instruction set. This parallel operation on data elements accelerates processing.
As noted above, MAC operations are used to accelerate various applications. In addition to speed, it would be desirable to have an architecture that is capable of handling multiply and accumulate operations for different-sized operands as required by the instruction (i.e., 8×8 operations, 16×16 operations, etc.). It would also be desirable to be able to retrieve individual results of MAC operations and clear the corresponding accumulator. In addition, it would be advantageous to have a MAC unit which could provide the cross-product of operands, pack results into one register, and shift results where desired.